Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate Dielectric
We propose double-gated n-type WSe<sub>2</sub> FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO<sub>2</sub> ALD on an Al<sub>2</sub>O<sub>3</sub> seed layer obtained from the evap...
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
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| Online Access: | https://ieeexplore.ieee.org/document/8790754/ |
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| author | Nicolo Oliva Yury Yu Illarionov Emanuele A. Casu Matteo Cavalieri Theresia Knobloch Tibor Grasser Adrian M. Ionescu |
| author_facet | Nicolo Oliva Yury Yu Illarionov Emanuele A. Casu Matteo Cavalieri Theresia Knobloch Tibor Grasser Adrian M. Ionescu |
| author_sort | Nicolo Oliva |
| collection | DOAJ |
| description | We propose double-gated n-type WSe<sub>2</sub> FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO<sub>2</sub> ALD on an Al<sub>2</sub>O<sub>3</sub> seed layer obtained from the evaporation and oxidation by air exposure of a 1.5 nm Al layer. When operated under back gate control, the fabricated WSe<sub>2</sub> FETs behave as n-type enhancement transistors with ON/OFF current ratios exceeding 6 orders of magnitude and a ON current close to 1 μA/μm at a drain bias of 100 mV. An applied negative top gate bias determines a much steeper turn-on of the back gated transfer characteristic and a reduction of the observed hysteresis. Top gate devices behave as n-type depletion FETs, reaching a ION/IOFF ratio larger than 10<sup>6</sup> under positive bias applied to the back gate. The electron mobility, extracted using the Y-function method, was estimated to be 22.15 cm<sup>2</sup>V<sup>-1</sup>s<sup>-1</sup> under a drain bias of 1 mV. We characterize the hysteresis dynamics in our devices, demonstrating a substantial improvement with respect to comparable top gated MoS<sub>2</sub> FETs. |
| first_indexed | 2024-12-13T13:23:16Z |
| format | Article |
| id | doaj.art-c82e16e2813f4c9a8053419461f0c56d |
| institution | Directory Open Access Journal |
| issn | 2168-6734 |
| language | English |
| last_indexed | 2024-12-13T13:23:16Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Journal of the Electron Devices Society |
| spelling | doaj.art-c82e16e2813f4c9a8053419461f0c56d2022-12-21T23:44:21ZengIEEEIEEE Journal of the Electron Devices Society2168-67342019-01-0171163116910.1109/JEDS.2019.29337458790754Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate DielectricNicolo Oliva0https://orcid.org/0000-0001-5866-799XYury Yu Illarionov1https://orcid.org/0000-0003-4323-1389Emanuele A. Casu2https://orcid.org/0000-0001-7349-5786Matteo Cavalieri3Theresia Knobloch4https://orcid.org/0000-0001-5156-9510Tibor Grasser5https://orcid.org/0000-0001-6536-2238Adrian M. Ionescu6Nanoelectronics Devices Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, SwitzerlandInstitute for Microelectronics, TU Wien, Vienna, AustriaNanoelectronics Devices Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, SwitzerlandNanoelectronics Devices Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, SwitzerlandInstitute for Microelectronics, TU Wien, Vienna, AustriaInstitute for Microelectronics, TU Wien, Vienna, AustriaNanoelectronics Devices Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, SwitzerlandWe propose double-gated n-type WSe<sub>2</sub> FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO<sub>2</sub> ALD on an Al<sub>2</sub>O<sub>3</sub> seed layer obtained from the evaporation and oxidation by air exposure of a 1.5 nm Al layer. When operated under back gate control, the fabricated WSe<sub>2</sub> FETs behave as n-type enhancement transistors with ON/OFF current ratios exceeding 6 orders of magnitude and a ON current close to 1 μA/μm at a drain bias of 100 mV. An applied negative top gate bias determines a much steeper turn-on of the back gated transfer characteristic and a reduction of the observed hysteresis. Top gate devices behave as n-type depletion FETs, reaching a ION/IOFF ratio larger than 10<sup>6</sup> under positive bias applied to the back gate. The electron mobility, extracted using the Y-function method, was estimated to be 22.15 cm<sup>2</sup>V<sup>-1</sup>s<sup>-1</sup> under a drain bias of 1 mV. We characterize the hysteresis dynamics in our devices, demonstrating a substantial improvement with respect to comparable top gated MoS<sub>2</sub> FETs.https://ieeexplore.ieee.org/document/8790754/WSe₂double-gated FETs2D materialsfield-effect devicesatomic layer deposition |
| spellingShingle | Nicolo Oliva Yury Yu Illarionov Emanuele A. Casu Matteo Cavalieri Theresia Knobloch Tibor Grasser Adrian M. Ionescu Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate Dielectric IEEE Journal of the Electron Devices Society WSe₂ double-gated FETs 2D materials field-effect devices atomic layer deposition |
| title | Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate Dielectric |
| title_full | Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate Dielectric |
| title_fullStr | Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate Dielectric |
| title_full_unstemmed | Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate Dielectric |
| title_short | Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate Dielectric |
| title_sort | hysteresis dynamics in double gated n type wse sub 2 sub fets with high k top gate dielectric |
| topic | WSe₂ double-gated FETs 2D materials field-effect devices atomic layer deposition |
| url | https://ieeexplore.ieee.org/document/8790754/ |
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