Hysteresis Dynamics in Double-Gated n-Type WSe<sub>2</sub> FETs With High-k Top Gate Dielectric
We propose double-gated n-type WSe<sub>2</sub> FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO<sub>2</sub> ALD on an Al<sub>2</sub>O<sub>3</sub> seed layer obtained from the evap...
Main Authors: | Nicolo Oliva, Yury Yu Illarionov, Emanuele A. Casu, Matteo Cavalieri, Theresia Knobloch, Tibor Grasser, Adrian M. Ionescu |
---|---|
Format: | Article |
Language: | English |
Published: |
IEEE
2019-01-01
|
Series: | IEEE Journal of the Electron Devices Society |
Subjects: | |
Online Access: | https://ieeexplore.ieee.org/document/8790754/ |
Similar Items
-
The Impact of Hysteresis Effect on Device Characteristic and Reliability for Various Fin-Widths Tri-Gate Hf<sub>0.5</sub>Zr<sub>0.5</sub>O<sub>2</sub> Ferroelectric FinFET
by: Wen-Qi Zhang, et al.
Published: (2023-04-01) -
Circuit simulation of floating-gate FET (FGFET) for logic application
by: Yunjae Kim, et al.
Published: (2023-12-01) -
Phenomenological Model of Gate-Dependent Kink in I-V Characteristics of MoS<sub>2</sub> Double-Gate FETs
by: Michael A. Rodder, et al.
Published: (2021-01-01) -
Enhanced Hole Injection Into Single Layer WSe<sub>2</sub>
by: Michael A. Rodder, et al.
Published: (2018-01-01) -
Comparison of Temperature Dependent Carrier Transport in FinFET and Gate-All-Around Nanowire FET
by: Soohyun Kim, et al.
Published: (2020-04-01)