Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems

Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems

Charge‐trapping tunnel field effect transistors (CT‐TFETs) are experimentally demonstrated, and their array operations are discussed for low‐power large‐scale neuromorphic applications. CT‐TFETs cointegrated with charge‐trapping metal–oxide–semiconductor FETs (CT‐MOSFETs) through complementary metal...

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Bibliographic Details
Main Authors: Jae Seung Woo, Chae Lin Jung, Ki Ryung Nam, Woo Young Choi
Format: Article
Language:English
Published: Wiley 2023-11-01
Series:Advanced Intelligent Systems
Subjects:
charge-trapping TFETs
lower voltage drop
neuromorphic hardware architectures
Online Access:https://doi.org/10.1002/aisy.202300242

Internet

https://doi.org/10.1002/aisy.202300242

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