Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems

Charge‐trapping tunnel field effect transistors (CT‐TFETs) are experimentally demonstrated, and their array operations are discussed for low‐power large‐scale neuromorphic applications. CT‐TFETs cointegrated with charge‐trapping metal–oxide–semiconductor FETs (CT‐MOSFETs) through complementary metal...

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Main Authors: Jae Seung Woo, Chae Lin Jung, Ki Ryung Nam, Woo Young Choi
Format: Article
Language:English
Published: Wiley 2023-11-01
Series:Advanced Intelligent Systems
Subjects:
Online Access:https://doi.org/10.1002/aisy.202300242
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author Jae Seung Woo
Chae Lin Jung
Ki Ryung Nam
Woo Young Choi
author_facet Jae Seung Woo
Chae Lin Jung
Ki Ryung Nam
Woo Young Choi
author_sort Jae Seung Woo
collection DOAJ
description Charge‐trapping tunnel field effect transistors (CT‐TFETs) are experimentally demonstrated, and their array operations are discussed for low‐power large‐scale neuromorphic applications. CT‐TFETs cointegrated with charge‐trapping metal–oxide–semiconductor FETs (CT‐MOSFETs) through complementary metal–oxide–semiconductor logic process exhibit ≈2,000× lower on‐current (Ion) and ≈3,000× lower off‐current (Ioff) than CT‐MOSFETs, rendering them suitable for high‐accuracy large‐scale neuromorphic systems. According to the experimental and simulation results, CT‐TFETs outperform CT‐MOSFETs in terms of more accurate analog vector‐matrix multiplication than that of CT‐MOSFETs due to the following two reasons: first, CT‐TFETs feature a lower voltage (IR) drop resulting from lower Ion than that of CT‐MOSFETs. Second, the former is more robust to the IR drops than the latter due to weak channel length modulation. For example, unlike CT‐MOSFETs, the proposed CT‐TFETs exhibit ignorable weight degradation in spite of the 1 Ω wire resistance. CT‐TFET arrays show ≈700× lower power consumption and ≈10% higher MNIST classification accuracy than CT‐MOSFET arrays, making CT‐TFET arrays promising for extensive and versatile neuromorphic computing applications.
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spelling doaj.art-c862d47ee9564b9fac49d11c55727b192023-11-27T21:14:08ZengWileyAdvanced Intelligent Systems2640-45672023-11-01511n/an/a10.1002/aisy.202300242Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic SystemsJae Seung Woo0Chae Lin Jung1Ki Ryung Nam2Woo Young Choi3Department of Electrical and Computer Engineering and the Inter-university Semiconductor University Research Center (ISRC) Seoul National University Gwanak-gu Seoul 08826 Republic of KoreaDepartment of Electronic Engineering Sogang University Mapo-gu Seoul 04107 Republic of KoreaDepartment of Electronic Engineering Sogang University Mapo-gu Seoul 04107 Republic of KoreaDepartment of Electrical and Computer Engineering and the Inter-university Semiconductor University Research Center (ISRC) Seoul National University Gwanak-gu Seoul 08826 Republic of KoreaCharge‐trapping tunnel field effect transistors (CT‐TFETs) are experimentally demonstrated, and their array operations are discussed for low‐power large‐scale neuromorphic applications. CT‐TFETs cointegrated with charge‐trapping metal–oxide–semiconductor FETs (CT‐MOSFETs) through complementary metal–oxide–semiconductor logic process exhibit ≈2,000× lower on‐current (Ion) and ≈3,000× lower off‐current (Ioff) than CT‐MOSFETs, rendering them suitable for high‐accuracy large‐scale neuromorphic systems. According to the experimental and simulation results, CT‐TFETs outperform CT‐MOSFETs in terms of more accurate analog vector‐matrix multiplication than that of CT‐MOSFETs due to the following two reasons: first, CT‐TFETs feature a lower voltage (IR) drop resulting from lower Ion than that of CT‐MOSFETs. Second, the former is more robust to the IR drops than the latter due to weak channel length modulation. For example, unlike CT‐MOSFETs, the proposed CT‐TFETs exhibit ignorable weight degradation in spite of the 1 Ω wire resistance. CT‐TFET arrays show ≈700× lower power consumption and ≈10% higher MNIST classification accuracy than CT‐MOSFET arrays, making CT‐TFET arrays promising for extensive and versatile neuromorphic computing applications.https://doi.org/10.1002/aisy.202300242charge-trapping TFETslower voltage dropneuromorphic hardware architectures
spellingShingle Jae Seung Woo
Chae Lin Jung
Ki Ryung Nam
Woo Young Choi
Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems
Advanced Intelligent Systems
charge-trapping TFETs
lower voltage drop
neuromorphic hardware architectures
title Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems
title_full Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems
title_fullStr Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems
title_full_unstemmed Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems
title_short Logic‐Compatible Charge‐Trapping Tunnel Field Effect Transistors for Low‐Power, High‐Accuracy, and Large‐Scale Neuromorphic Systems
title_sort logic compatible charge trapping tunnel field effect transistors for low power high accuracy and large scale neuromorphic systems
topic charge-trapping TFETs
lower voltage drop
neuromorphic hardware architectures
url https://doi.org/10.1002/aisy.202300242
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