Asynchronous carry select adders

Asynchronous carry select adders

This paper discusses the standard cell based designs of asynchronous carry select adders (CSLAs) corresponding to strong-indication, weak-indication, and early output timing regimes realized using a delay-insensitive dual-rail code for data representation and processing, and a 4-phase return-to-zero...

Full description

Bibliographic Details
Main Author: P. Balasubramanian
Format: Article
Language:English
Published: Elsevier 2017-06-01
Series:Engineering Science and Technology, an International Journal
Subjects:
Asynchronous circuits
Full adder
Carry select adder
Indication
Early output
ASIC
Standard cells
CMOS
Online Access:http://www.sciencedirect.com/science/article/pii/S2215098616311272

Internet

http://www.sciencedirect.com/science/article/pii/S2215098616311272

Similar Items