Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language

Parameterizable Design on Convolutional Neural Networks Using Chisel Hardware Construction Language

This paper presents a parameterizable design generator on convolutional neural networks (CNNs) using the Chisel hardware construction language (HCL). By parameterizing structural designs such as the streaming width, pooling layer type, and floating point precision, multiple register–transfer level (...

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Bibliographic Details
Main Authors: Mukesh Chowdary Madineni, Mario Vega, Xiaokun Yang
Format: Article
Language:English
Published: MDPI AG 2023-02-01
Series:Micromachines
Subjects:
convolutional neural network (CNN)
Chisel HCL
FPGA
register–transfer level
Verilog HDL
Online Access:https://www.mdpi.com/2072-666X/14/3/531

Internet

https://www.mdpi.com/2072-666X/14/3/531

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