Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators

Abstract New theoretical lower bounds for the number of operators needed in fixed-point constant multiplication blocks are presented. The multipliers are constructed with the shift-and-add approach, where every arithmetic operation is pipelined, and with the generalization that n-input pipelined add...

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Bibliographic Details
Main Authors: Miriam Guadalupe Cruz Jiménez, Uwe Meyer Baese, Gordana Jovanovic Dolecek
Format: Article
Language:English
Published: SpringerOpen 2017-05-01
Series:EURASIP Journal on Advances in Signal Processing
Subjects:
SCM
MCM
FPGA
Multiplication
Lower bound
Online Access:http://link.springer.com/article/10.1186/s13634-017-0466-z

Internet

http://link.springer.com/article/10.1186/s13634-017-0466-z

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