Theoretical lower bounds for parallel pipelined shift-and-add constant multiplications with n-input arithmetic operators
Abstract New theoretical lower bounds for the number of operators needed in fixed-point constant multiplication blocks are presented. The multipliers are constructed with the shift-and-add approach, where every arithmetic operation is pipelined, and with the generalization that n-input pipelined add...
Main Authors: | , , |
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Format: | Article |
Language: | English |
Published: |
SpringerOpen
2017-05-01
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Series: | EURASIP Journal on Advances in Signal Processing |
Subjects: | |
Online Access: | http://link.springer.com/article/10.1186/s13634-017-0466-z |
Summary: | Abstract New theoretical lower bounds for the number of operators needed in fixed-point constant multiplication blocks are presented. The multipliers are constructed with the shift-and-add approach, where every arithmetic operation is pipelined, and with the generalization that n-input pipelined additions/subtractions are allowed, along with pure pipelining registers. These lower bounds, tighter than the state-of-the-art theoretical limits, are particularly useful in early design stages for a quick assessment in the hardware utilization of low-cost constant multiplication blocks implemented in the newest families of field programmable gate array (FPGA) integrated circuits. |
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ISSN: | 1687-6180 |