2T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computing
<p indent="0mm">In-memory computing is an alternative method to effectively accelerate the massive data-computing tasks of artificial intelligence (AI) and break the memory wall. In this work, we propose a 2T1C DRAM structure for in-memory computing. It integrates a monolayer graphen...
| Main Authors: | , , , , , , , , |
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| Format: | Article |
| Language: | English |
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Science Press
2023-06-01
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| Series: | National Science Open |
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| Online Access: | https://www.sciengine.com/doi/10.1360/nso/20220071 |
| _version_ | 1797778339215179776 |
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| author | Gou Saifei Wang Yin Dong Xiangqi Xu Zihan Wang Xinyu Sun Qicheng Xie Yufeng Zhou Peng Bao Wenzhong |
| author_facet | Gou Saifei Wang Yin Dong Xiangqi Xu Zihan Wang Xinyu Sun Qicheng Xie Yufeng Zhou Peng Bao Wenzhong |
| author_sort | Gou Saifei |
| collection | DOAJ |
| description | <p indent="0mm">In-memory computing is an alternative method to effectively accelerate the massive data-computing tasks of artificial intelligence (AI) and break the memory wall. In this work, we propose a 2T1C DRAM structure for in-memory computing. It integrates a monolayer graphene transistor, a monolayer MoS<sub>2</sub> transistor, and a capacitor in a two-transistor-one-capacitor (2T1C) configuration. In this structure, the storage node is in a similar position to that of one-transistor-one-capacitor (1T1C) dynamic random-access memory (DRAM), while an additional graphene transistor is used to accomplish the non-destructive readout of the stored information. Furthermore, the ultralow leakage current of the MoS<sub>2</sub> transistor enables the storage of multi-level voltages on the capacitor with a long retention time. The stored charges can effectually tune the channel conductance of the graphene transistor due to its excellent linearity so that linear analog multiplication can be realized. Because of the almost unlimited cycling endurance of DRAM, our 2T1C DRAM has great potential for <italic>in situ</italic> training and recognition, which can significantly improve the recognition accuracy of neural networks.</p> |
| first_indexed | 2024-03-12T23:16:49Z |
| format | Article |
| id | doaj.art-cb03d18c262e4ee784bd574d23ec35da |
| institution | Directory Open Access Journal |
| issn | 2097-1168 |
| language | English |
| last_indexed | 2024-03-12T23:16:49Z |
| publishDate | 2023-06-01 |
| publisher | Science Press |
| record_format | Article |
| series | National Science Open |
| spelling | doaj.art-cb03d18c262e4ee784bd574d23ec35da2023-07-17T06:18:41ZengScience PressNational Science Open2097-11682023-06-01210.1360/nso/20220071eb33e6422T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computingGou Saifei0Wang Yin1Dong Xiangqi2Xu Zihan3Wang Xinyu4Sun Qicheng5Xie Yufeng6Zhou Peng7Bao Wenzhong8["State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Zhangjiang Fudan International Innovation Center, Shanghai 200433, China"]["State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Zhangjiang Fudan International Innovation Center, Shanghai 200433, China"]["State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Zhangjiang Fudan International Innovation Center, Shanghai 200433, China"]["Shenzhen Six Carbon Technology, Shenzhen 518055, China"]["State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Zhangjiang Fudan International Innovation Center, Shanghai 200433, China"]["State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Zhangjiang Fudan International Innovation Center, Shanghai 200433, China"]["State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Zhangjiang Fudan International Innovation Center, Shanghai 200433, China"]["State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Zhangjiang Fudan International Innovation Center, Shanghai 200433, China"]["State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Zhangjiang Fudan International Innovation Center, Shanghai 200433, China"]<p indent="0mm">In-memory computing is an alternative method to effectively accelerate the massive data-computing tasks of artificial intelligence (AI) and break the memory wall. In this work, we propose a 2T1C DRAM structure for in-memory computing. It integrates a monolayer graphene transistor, a monolayer MoS<sub>2</sub> transistor, and a capacitor in a two-transistor-one-capacitor (2T1C) configuration. In this structure, the storage node is in a similar position to that of one-transistor-one-capacitor (1T1C) dynamic random-access memory (DRAM), while an additional graphene transistor is used to accomplish the non-destructive readout of the stored information. Furthermore, the ultralow leakage current of the MoS<sub>2</sub> transistor enables the storage of multi-level voltages on the capacitor with a long retention time. The stored charges can effectually tune the channel conductance of the graphene transistor due to its excellent linearity so that linear analog multiplication can be realized. Because of the almost unlimited cycling endurance of DRAM, our 2T1C DRAM has great potential for <italic>in situ</italic> training and recognition, which can significantly improve the recognition accuracy of neural networks.</p>https://www.sciengine.com/doi/10.1360/nso/20220071molybdenum disulfide (MoS<sub>2</sub>)grapheneDRAMin-memory computing |
| spellingShingle | Gou Saifei Wang Yin Dong Xiangqi Xu Zihan Wang Xinyu Sun Qicheng Xie Yufeng Zhou Peng Bao Wenzhong 2T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computing National Science Open molybdenum disulfide (MoS<sub>2</sub>) graphene DRAM in-memory computing |
| title | 2T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computing |
| title_full | 2T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computing |
| title_fullStr | 2T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computing |
| title_full_unstemmed | 2T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computing |
| title_short | 2T1C DRAM based on semiconducting MoS<sub>2</sub> and semimetallic graphene for in-memory computing |
| title_sort | 2t1c dram based on semiconducting mos sub 2 sub and semimetallic graphene for in memory computing |
| topic | molybdenum disulfide (MoS<sub>2</sub>) graphene DRAM in-memory computing |
| url | https://www.sciengine.com/doi/10.1360/nso/20220071 |
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