A Device Design for 5 nm Logic FinFET Technology

A Device Design for 5 nm Logic FinFET Technology

With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22...

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Bibliographic Details
Main Authors: Yu Ding, Yongfeng Cao, Xin Luo, Enming Shang, Shaojian Hu, Shoumian Chen, Yuhang Zhao
Format: Article
Language:English
Published: JommPublish 2020-03-01
Series:Journal of Microelectronic Manufacturing
Subjects:
5nm finfet
brief process flow
key dimensions
simulated device dc/ac performance
ro ppa performance
Online Access:http://www.jommpublish.org/p/50/

Internet

http://www.jommpublish.org/p/50/

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