A Device Design for 5 nm Logic FinFET Technology
With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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JommPublish
2020-03-01
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| Series: | Journal of Microelectronic Manufacturing |
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| Online Access: | http://www.jommpublish.org/p/50/ |
| _version_ | 1819028304614653952 |
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| author | Yu Ding Yongfeng Cao Xin Luo Enming Shang Shaojian Hu Shoumian Chen Yuhang Zhao |
| author_facet | Yu Ding Yongfeng Cao Xin Luo Enming Shang Shaojian Hu Shoumian Chen Yuhang Zhao |
| author_sort | Yu Ding |
| collection | DOAJ |
| description | With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node. The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates. Due to the relatively more mature process and rich learning of the device physics, the FinFET is still extended to 5 nm technology node. In this paper, we proposed a 5 nm FINFET device, which is based on typical 5 nm logic design rules. To achieve the challenging device performance target, which is around 15% speed gain or 25% power reduction against the 7 nm device, we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability. Based on our preferred device architecture, we provide our brief process flow, key dimensions, and simulated device DC/AC performance, like Vt, Idsat, SS, DIBL and parasitic parameters. As a part of the final evaluation, RO simulation result has been checked, which demonstrates that the Performance Per Area (PPA) is close to industry reference 5 nm performance. |
| first_indexed | 2024-12-21T05:56:14Z |
| format | Article |
| id | doaj.art-cbc0c74569e240d19fbd945b23fbc48f |
| institution | Directory Open Access Journal |
| issn | 2578-3769 2578-3769 |
| language | English |
| last_indexed | 2024-12-21T05:56:14Z |
| publishDate | 2020-03-01 |
| publisher | JommPublish |
| record_format | Article |
| series | Journal of Microelectronic Manufacturing |
| spelling | doaj.art-cbc0c74569e240d19fbd945b23fbc48f2022-12-21T19:13:52ZengJommPublishJournal of Microelectronic Manufacturing2578-37692578-37692020-03-01311610.33079/jomm.20030105A Device Design for 5 nm Logic FinFET TechnologyYu Ding 0Yongfeng Cao1Xin Luo2Enming Shang3Shaojian Hu4Shoumian Chen5Yuhang Zhao6Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai, China 201210Shanghai Huali Microelectronics Corporation, Zu Chongzhi Road, Pudong New Area, Shanghai, China, No 1399Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai, China 201210Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai, China 201210Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai, China 201210Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai, China 201210Shanghai Integrated Circuit Research and Development Center, No, ., 497, Gaosi Road, Pudong New Area, Shanghai, China 201210With the continuous scaling in conventional CMOS technologies, the planar MOSFET device is limited by the severe short-channel-effect (SCE), Multi-gate FETs (MuG-FET) such as FinFETs and Nanowire, Nanosheet devices have emerged as the most promising candidates to extend the CMOS scaling beyond sub-22 nm node. The multi-gate structure has better short channel behaviors due to enhanced control from the multiple gates. Due to the relatively more mature process and rich learning of the device physics, the FinFET is still extended to 5 nm technology node. In this paper, we proposed a 5 nm FINFET device, which is based on typical 5 nm logic design rules. To achieve the challenging device performance target, which is around 15% speed gain or 25% power reduction against the 7 nm device, we have performed an optimization on the process parameters and iterate through device simulation with the consideration of current process capability. Based on our preferred device architecture, we provide our brief process flow, key dimensions, and simulated device DC/AC performance, like Vt, Idsat, SS, DIBL and parasitic parameters. As a part of the final evaluation, RO simulation result has been checked, which demonstrates that the Performance Per Area (PPA) is close to industry reference 5 nm performance.http://www.jommpublish.org/p/50/5nm finfetbrief process flowkey dimensionssimulated device dc/ac performancero ppa performance |
| spellingShingle | Yu Ding Yongfeng Cao Xin Luo Enming Shang Shaojian Hu Shoumian Chen Yuhang Zhao A Device Design for 5 nm Logic FinFET Technology Journal of Microelectronic Manufacturing 5nm finfet brief process flow key dimensions simulated device dc/ac performance ro ppa performance |
| title | A Device Design for 5 nm Logic FinFET Technology |
| title_full | A Device Design for 5 nm Logic FinFET Technology |
| title_fullStr | A Device Design for 5 nm Logic FinFET Technology |
| title_full_unstemmed | A Device Design for 5 nm Logic FinFET Technology |
| title_short | A Device Design for 5 nm Logic FinFET Technology |
| title_sort | device design for 5 nm logic finfet technology |
| topic | 5nm finfet brief process flow key dimensions simulated device dc/ac performance ro ppa performance |
| url | http://www.jommpublish.org/p/50/ |
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