A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments
This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2020-10-01
|
| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9268/10/4/35 |
| _version_ | 1797549550413545472 |
|---|---|
| author | Federico Fary Andrea Baschirotto |
| author_facet | Federico Fary Andrea Baschirotto |
| author_sort | Federico Fary |
| collection | DOAJ |
| description | This paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order to achieve very low-power and high-speed performances. The proposed architecture does not require an internal clock or pre-charge phase, which usually increase the power request and slow down data searches. On the other hand, the dedicated solutions are exploited in order to minimize parasitic layout-induced capacitances in the single-bit cell, further reducing the power consumption. The prototype device, named CAM-28CB, is integrated in the deeply downscaled 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) Bulk (28CB) technology. In this way, the high transistor transition frequency and the intrinsic lower parasitic capacitances allow the system speed to be improved. Furthermore, the high radiation hardness of this technology node (up to 1Grad TID), together with the CAM-28CB high-speed and low-power performances, makes this device suitable for High-Energy Physics experiments, such as ATLAS (A Toroidal LHC ApparatuS) at Large Hadron Collider (LHC). The prototype operates at a frequency of up to 100 MHz and consumes 46.86 µW. The total area occupancy is 1702 µm<sup>2</sup> for 1.152 kb memory bit cells. The device operates with a single supply voltage of 1 V and achieves 0.41 fJ/bit/search Figure-of-Merit. |
| first_indexed | 2024-03-10T15:17:13Z |
| format | Article |
| id | doaj.art-cc087b8183f143f18ed877a7c5b62f9b |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-03-10T15:17:13Z |
| publishDate | 2020-10-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-cc087b8183f143f18ed877a7c5b62f9b2023-11-20T18:52:51ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682020-10-011043510.3390/jlpea10040035A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP ExperimentsFederico Fary0Andrea Baschirotto1Department of Physics and Italian National Institute for Nuclear Physics (INFN), University of Milano-Bicocca, 20126 Milan, ItalyDepartment of Physics and Italian National Institute for Nuclear Physics (INFN), University of Milano-Bicocca, 20126 Milan, ItalyThis paper presents a transistor-level design with extensive experimental validation of a Content Addressable Memory (CAM), based on an eXclusive OR (XOR) single-bit cell. This design exploits a dedicated architecture and a fully custom approach (both in the schematic and the layout phase), in order to achieve very low-power and high-speed performances. The proposed architecture does not require an internal clock or pre-charge phase, which usually increase the power request and slow down data searches. On the other hand, the dedicated solutions are exploited in order to minimize parasitic layout-induced capacitances in the single-bit cell, further reducing the power consumption. The prototype device, named CAM-28CB, is integrated in the deeply downscaled 28 nm Complementary Metal-Oxide-Semiconductor (CMOS) Bulk (28CB) technology. In this way, the high transistor transition frequency and the intrinsic lower parasitic capacitances allow the system speed to be improved. Furthermore, the high radiation hardness of this technology node (up to 1Grad TID), together with the CAM-28CB high-speed and low-power performances, makes this device suitable for High-Energy Physics experiments, such as ATLAS (A Toroidal LHC ApparatuS) at Large Hadron Collider (LHC). The prototype operates at a frequency of up to 100 MHz and consumes 46.86 µW. The total area occupancy is 1702 µm<sup>2</sup> for 1.152 kb memory bit cells. The device operates with a single supply voltage of 1 V and achieves 0.41 fJ/bit/search Figure-of-Merit.https://www.mdpi.com/2079-9268/10/4/35associative memorycontent addressable memorydigital integrated circuitsCMOS technologylow-power electronics |
| spellingShingle | Federico Fary Andrea Baschirotto A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments Journal of Low Power Electronics and Applications associative memory content addressable memory digital integrated circuits CMOS technology low-power electronics |
| title | A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments |
| title_full | A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments |
| title_fullStr | A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments |
| title_full_unstemmed | A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments |
| title_short | A 100 MHz 0.41 fJ/(Bit∙Search) 28 nm CMOS-Bulk Content Addressable Memory for HEP Experiments |
| title_sort | 100 mhz 0 41 fj bit∙search 28 nm cmos bulk content addressable memory for hep experiments |
| topic | associative memory content addressable memory digital integrated circuits CMOS technology low-power electronics |
| url | https://www.mdpi.com/2079-9268/10/4/35 |
| work_keys_str_mv | AT federicofary a100mhz041fjbitsearch28nmcmosbulkcontentaddressablememoryforhepexperiments AT andreabaschirotto a100mhz041fjbitsearch28nmcmosbulkcontentaddressablememoryforhepexperiments AT federicofary 100mhz041fjbitsearch28nmcmosbulkcontentaddressablememoryforhepexperiments AT andreabaschirotto 100mhz041fjbitsearch28nmcmosbulkcontentaddressablememoryforhepexperiments |