Novel BIST Solution to Test the TSV Interconnects in 3D Stacked IC’s
This paper proposes a novel technique of TSV BIST repair that targets the design yield and various test challenges of three-dimensional integrated circuits (3D stacked ICs). The proposed methodology is efficient to cover the various faults during the fabrication, the interconnect breakages, shorts,...
| Main Authors: | , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2023-02-01
|
| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/12/4/908 |