Hardware Reduction for FSMs With Extended State Codes

Hardware Reduction for FSMs With Extended State Codes

A method is proposed for reducing chip area occupied by logic circuits of FPGA-based Mealy finite state machines (FSMs). The proposed method aims at optimization of FSM circuits implemented with look-up table (LUT) elements of FPGA chip. The proposed method combines positive features of such state a...

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Bibliographic Details
Main Authors: Alexander Barkalov, Larysa Titarenko, Kamil Mielcarek, Malgorzata Mazurkiewicz
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
Mealy FSM
FPGA
LUT count
synthesis
extended state codes
composite state codes
Online Access:https://ieeexplore.ieee.org/document/10466758/

Internet

https://ieeexplore.ieee.org/document/10466758/

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