10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive
In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control cir...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-02-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/4/624 |
| _version_ | 1797480907484954624 |
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| author | Guo-Ming Sung Chong-Cheng Huang Xiong Xiao Shih-Ying Hsu |
| author_facet | Guo-Ming Sung Chong-Cheng Huang Xiong Xiao Shih-Ying Hsu |
| author_sort | Guo-Ming Sung |
| collection | DOAJ |
| description | In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm<sup>2</sup>, respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC. |
| first_indexed | 2024-03-09T22:06:55Z |
| format | Article |
| id | doaj.art-cf04796b0cbd427da4cbda982965b81a |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T22:06:55Z |
| publishDate | 2022-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-cf04796b0cbd427da4cbda982965b81a2023-11-23T19:40:20ZengMDPI AGElectronics2079-92922022-02-0111462410.3390/electronics1104062410-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor DriveGuo-Ming Sung0Chong-Cheng Huang1Xiong Xiao2Shih-Ying Hsu3Department of Electrical Engineering, National Taipei University of Technology, Taipei 10608, TaiwanDepartment of Electrical Engineering, National Taipei University of Technology, Taipei 10608, TaiwanDepartment of Mechanical Engineering, University of Science and Technology Beijing, Beijing 100083, ChinaDepartment of Electrical Engineering, National Taipei University of Technology, Taipei 10608, TaiwanIn this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm<sup>2</sup>, respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC.https://www.mdpi.com/2079-9292/11/4/624analog-to-digital converter (ADC)brushless direct current (BLDC) motorbootstrapped switchcharge pump (CP)digital-to-analog converter (DAC)dynamic comparator |
| spellingShingle | Guo-Ming Sung Chong-Cheng Huang Xiong Xiao Shih-Ying Hsu 10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive Electronics analog-to-digital converter (ADC) brushless direct current (BLDC) motor bootstrapped switch charge pump (CP) digital-to-analog converter (DAC) dynamic comparator |
| title | 10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive |
| title_full | 10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive |
| title_fullStr | 10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive |
| title_full_unstemmed | 10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive |
| title_short | 10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive |
| title_sort | 10 bit 5 ms s successive approximation register analog to digital converter with a phase locked loop and modified bootstrapped switch for a bldc motor drive |
| topic | analog-to-digital converter (ADC) brushless direct current (BLDC) motor bootstrapped switch charge pump (CP) digital-to-analog converter (DAC) dynamic comparator |
| url | https://www.mdpi.com/2079-9292/11/4/624 |
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