| Summary: | In this paper, a fractional frequency division phase-locked loop based on phase interpolation is proposed and implemented using the TSMC 0.11 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>m CMOS process. Compared with the conventional phase-locked loop, a digital time converter (DTC) module is added to this phase-locked loop, and the DTC module can reduce the fractional spurious by phase interpolation. The circuit and analysis method of this DTC module are given in this paper. Unlike the existing approaches, the proposed DTC is calibration-free, and the error introduced by it is only related to the DAC adopted in the DTC. In addition, the accuracy of the DTC is 8 bits. Finally, this paper verifies the proposed quantization noise reduction technique using a 0.11 <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>m CMOS process. The proposed FNPLL achieves the overall power consumption of 20.3 mW, the noise of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>117</mn><mspace width="4pt"></mspace></mrow></semantics></math></inline-formula>dBc/Hz@1 MHz and <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mo>−</mo><mn>138</mn><mspace width="4pt"></mspace></mrow></semantics></math></inline-formula>dBc/Hz<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mspace width="4pt"></mspace><mo>@</mo><mspace width="4pt"></mspace></mrow></semantics></math></inline-formula>10 MHz, and the RMS jitter of <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>0.860</mn><mspace width="4pt"></mspace></mrow></semantics></math></inline-formula>ps. The area of the proposed FDIV is <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>60</mn><mo>×</mo><mn>245</mn><mspace width="4pt"></mspace><mi mathvariant="sans-serif">μ</mi></mrow></semantics></math></inline-formula>m<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><msup><mrow></mrow><mn>2</mn></msup></semantics></math></inline-formula>, and the power consumption is <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>1.356</mn><mspace width="4pt"></mspace></mrow></semantics></math></inline-formula>mW. The phase noise of the proposed FNPLL in the fractional division mode is just <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mrow><mn>2</mn><mspace width="4pt"></mspace></mrow></semantics></math></inline-formula>dB higher than that in the integer division mode.
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