Static power model for CMOS and FPGA circuits

Static power model for CMOS and FPGA circuits

Abstract In Ultra‐Low‐Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time‐consuming Spice simulations are used to measure the static power consumption. Herein, a technology‐independent static power estimatio...

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Bibliographic Details
Main Authors: Anas Razzaq, Andy Ye
Format: Article
Language:English
Published: Hindawi-IET 2021-07-01
Series:IET Computers & Digital Techniques
Subjects:
CMOS logic circuits
field programmable gate arrays
integrated circuit modelling
logic design
low‐power electronics
power consumption
Online Access:https://doi.org/10.1049/cdt2.12021

Internet

https://doi.org/10.1049/cdt2.12021

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