Static power model for CMOS and FPGA circuits

Static power model for CMOS and FPGA circuits

Abstract In Ultra‐Low‐Power (ULP) applications, power consumption is a key parameter for process independent architectural level design decisions. Traditionally, time‐consuming Spice simulations are used to measure the static power consumption. Herein, a technology‐independent static power estimatio...

Full description

Bibliographic Details
Main Authors:	Anas Razzaq, Andy Ye
Format:	Article
Language:	English
Published:	Hindawi-IET 2021-07-01
Series:	IET Computers & Digital Techniques
Subjects:	CMOS logic circuits field programmable gate arrays integrated circuit modelling logic design low‐power electronics power consumption
Online Access:	https://doi.org/10.1049/cdt2.12021

Similar Items

TVD‐PB logic circuit based on camouflaging circuit for IoT security
by: Yuejun Zhang, et al.
Published: (2022-01-01)

PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits
by: KIREI, B. S., et al.
Published: (2019-02-01)

Multi-directional matrix converter for low power application using field-programmable gate array
by: Toosi, Saman
Published: (2015)

Real time plate recognition for motorcycle using field programmable gate array
by: Mat Nong, Mohd Ali
Published: (2019)

Shortest path processor using FPGA /
by: 259595 Rizal Kasyrno Ghazali
Published: (1999)

Barcode reader in FPGA /
by: 370662 Leue, Ching Tsong
Published: (1998)

Lozenge optimization engine on FPGA for gate allocation system /
by: 189051 Noor Shafinaz Saad, et al.
Published: (2007)

Shrinking FPGA Static Power via Machine Learning-Based Power Gating and Enhanced Routing
by: Zeinab Seifoori, et al.
Published: (2021-01-01)

Challenges to adopting adiabatic circuits for systems‐on‐a‐chip
by: Krishnan S. Rengarajan, et al.
Published: (2021-09-01)

Lozenge optimization engine on FPGA for gate allocation system [electronic resource] /
by: 189051 Noor Shafinaz Saad, et al.
Published: (2007)

GateRL: Automated Circuit Design Framework of CMOS Logic Gates Using Reinforcement Learning
by: Hyoungsik Nam, et al.
Published: (2021-04-01)

Exploring FPGA Logic Block Architecture for Reduced Configuration Memory
by: HUSSAIN, F., et al.
Published: (2022-08-01)

A low power and soft error resilience guard‐gated Quartro‐based flip‐flop in 45 nm CMOS technology
by: Sabavat Satheesh Kumar, et al.
Published: (2021-09-01)

Design and Implementation of Asynchronous Processor on FPGA
by: Ziho Shin, et al.
Published: (2022-01-01)

Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS
by: David Bol
Published: (2011-01-01)

Automatic diagnosis of single fault in interconnect testing of SRAM‐based FPGA
by: T. Nirmalraj, et al.
Published: (2021-09-01)

Digital systems design with FPGAs and CPLDs /
by: 455125 Grout, Ian
Published: (2008)

Accurate dynamic power estimation for CMOS combinational logic circuits with real gate delay model
by: Omnia S. Fadl, et al.
Published: (2016-01-01)

AN OVERVIEW OF POWER DISSIPATION AND CONTROL TECHNIQUES IN CMOS TECHNOLOGY
by: N. B. ROMLI, et al.
Published: (2015-03-01)

High robustness energy- and area-efficient dynamic-voltage-scaling 4-phase 4-rail asynchronous-logic Network-on-Chip (ANoC)
by: Ho, Weng-Geng, et al.
Published: (2016)

Designing with FPGAs and CPLDs /
by: 240588 Zeidman, Bob
Published: (2002)

Development of software interface for shortest path processor [microfilm] /
by: Alagendra Prakash Jayaraman
Published: (2001)

Designing with FPGAs and CPLDs /
by: 378537 Jenkins, Jesse H.
Published: (1994)

Development of software interface for shortest path processor /
by: 238780 Alagendra Prakash Jayaraman
Published: (2001)

Implementation of ether interface for nios processor /
by: 372855 Edwin Edward
Published: (2006)

FPGA-based system design /
by: 377648 Wolf, Wayne Hendrix
Published: (2004)

Field programmable gate array (FPGA) implementation of data encryption standard (DES) /
by: 439988 Kong, Zhi Hui
Published: (1999)

A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique
by: Juan Jesus Ocampo-Hidalgo, et al.
Published: (2017-05-01)

Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication
by: Geetam Singh Tomar, et al.
Published: (2021-08-01)

Ultra-low-power CMOS ring oscillator with minimum power consumption of 2.9 pW using low-voltage biasing technique
by: Al-Shebanee Durgham
Published: (2024-02-01)

Programmable logic handbook : PLDs, CPLDs, and FPGAs /
by: 309677 Sharma, Ashok K.
Published: (1998)

FPGA-Based Hardware-in-the-Loop (HIL) Emulation of Power Electronics Circuit Using Device-Level Behavioral Modeling
by: Mohamed Baghdadi, et al.
Published: (2023-10-01)

Investigation on the divider circuits ... [et al.] / [mikrofilem]
by: 369369 Lai, Main Darh
Published: (1998)

Design of testable logic circuits /
by: 373238 Bennets, R. G.
Published: (1984)

An efficient 70 GHz divide‐by‐4 CMOS frequency divider employing low threshold devices
by: Zoltán Tibenszky, et al.
Published: (2021-07-01)

Fully FPGA‐based implementation of a modified control strategy for power electronic transformer in railway traction applications
by: Khalil Akbariavaz, et al.
Published: (2021-08-01)

Computer-aided analysis of static hazards for near-optimal design of asynchronous sequential logic circuits /
by: Mohamed Khalil Mohd. Hani 608642, et al.

Low-power design of nanometer FPGAs : architecture and EDA /
by: Hassan, Hassan A., 1979-, et al.
Published: (2010)

Characterizing a standard cell library for large scale design of memristive based signal processing
by: Abubaker Sasi, et al.
Published: (2022-01-01)

Checkability of the circuits in FPGA designs according to power dissipation
by: Antoniuk V. V., et al.
Published: (2019-04-01)