Formal Verification of Fault-Tolerant Hardware Designs

Formal Verification of Fault-Tolerant Hardware Designs

Digital circuits for space applications can suffer from operation failures due to radiation effects. Error detection and mitigation techniques are widely accepted solutions to improve dependability of digital circuits under Single Event Upsets (SEUs) and Single Event Transients (SETs). These solutio...

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Bibliographic Details
Main Authors: Luis Entrena, Antonio J. Sanchez-Clemente, Luis A. Garcia-Astudillo, Marta Portela-Garcia, Mario Garcia-Valderas, Almudena Lindoso, Roberto Sarmiento
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
Equivalence checking
fault tolerance
formal verification
error mitigation
Online Access:https://ieeexplore.ieee.org/document/10287308/

Internet

https://ieeexplore.ieee.org/document/10287308/

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