A Feasible Alternative to FDSOI and FinFET: Optimization of W/La<sub>2</sub>O<sub>3</sub>/Si Planar PMOS with 14 nm Gate-Length
At the 90-nm node, the rate of transistor miniaturization slows down due to challenges in overcoming the increased leakage current (<i>I<sub>off</sub></i>). The invention of high-k/metal gate technology at the 45-nm technology node was an enormous step forward in extending Mo...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2021-09-01
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| Series: | Materials |
| Subjects: | |
| Online Access: | https://www.mdpi.com/1996-1944/14/19/5721 |