A 60GS/s Two-Stage Sampler with a Linearity Calibration Loop for PAM-8 Receivers

In this article, we show a 60 GS/s two-stage 8 × 8 time-interleaved sampling circuit, where the second-stage nonlinearity can be controlled by using the voltage that optimizes the static distortions of the sampler. A calibration algorithm can extract the nonlinear contributions of the stages and com...

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Bibliographic Details
Main Authors: Alessio Di Pasquo, Enrico Monaco, Nicola Ghittori, Claudio Nani, Luca Fanucci
Format: Article
Language:English
Published: MDPI AG 2022-10-01
Series:Electronics
Subjects:
Online Access:https://www.mdpi.com/2079-9292/11/21/3484