A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

A 52-Gb/s Sub-1-pJ/bit PAM4 Receiver in 40-nm CMOS for Low-Power Interconnects

This article presents a quarter-rate source-synchronous PAM-4 receiver for energy-efficient chip-to-module communication. A novel single-stage multiple peaking continuous-time linear equalizer (MP-CTLE) using feedback enabled multiple peaking scheme for both high-frequency equalization (HF-EQ) and l...

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Bibliographic Details
Main Authors: Can Wang, Li Wang, Zhao Zhang, Milad Kalantari Mahmoudabadi, Weimin Shi, C. Patrick Yue
Format: Article
Language:English
Published: IEEE 2021-01-01
Series:IEEE Open Journal of Circuits and Systems
Subjects:
PAM4 receiver
wide bandwidth PLL
multiple peaking CTLE
energy efficient
quarter-rate source-synchronous receiver
Online Access:https://ieeexplore.ieee.org/document/9318040/

Internet

https://ieeexplore.ieee.org/document/9318040/

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