FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

FPGA Acceleration of 3GPP Channel Model Emulator for 5G New Radio

The channel model is by far the most computing intensive part of the link level simulations of multiple-input and multiple-output (MIMO) fifth-generation new radio (5GNR) communication systems. Simulation effort further increases when using more realistic geometry-based channel models, such as the t...

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Bibliographic Details
Main Authors: Nasir Ali Shah, Mihai T. Lazarescu, Roberto Quasso, Salvatore Scarpina, Luciano Lavagno
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Channel emulator
FPGA
fifth-generation new radio
hardware acceleration
high-level synthesis
Online Access:https://ieeexplore.ieee.org/document/9944632/

Internet

https://ieeexplore.ieee.org/document/9944632/

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