Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m)

Multiple Bit Error Tolerant Galois Field Architectures Over GF (2m)

Radiation induced transient faults like single event upsets (SEU) and multiple event upsets (MEU) in memories are well researched. As a result of the technology scaling, it is observed that the logic blocks are also vulnerable to malfunctioning when they are deployed in radiation prone environment....

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Bibliographic Details
Main Authors: Mahesh Poolakkaparambil, Jimson Mathew, Abusaleh Jabir
Format: Article
Language:English
Published: MDPI AG 2012-06-01
Series:Electronics
Subjects:
Galois Field (GF)
cryptography
Single Event Upset (SEU)
Multiple Event Upset (MEU)
Triple Modular Redundancy (TMR)
error correction
fault tolerance
Online Access:http://www.mdpi.com/2079-9292/1/1/3

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http://www.mdpi.com/2079-9292/1/1/3

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