Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs

Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and specification do not match, the CTS result will be wrong. Many users use licensed electronic desig...

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Bibliographic Details
Main Authors: Nayoung Kwon, Daejin Park
Format: Article
Language:English
Published: MDPI AG 2023-10-01
Series:Electronics
Subjects:
chip design
clock tree synthesis (CTS)
place and route (P&R)
licensed electronic design automation tool (EDA)
buffer insertion
clock skew
Online Access:https://www.mdpi.com/2079-9292/12/20/4340

Internet

https://www.mdpi.com/2079-9292/12/20/4340

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