Shallow Clock Tree Pre-Estimation for Designing Clock Tree Synthesizable Verilog RTLs
Clock tree synthesis (CTS) is an important process in determining overall chip timing and power consumption. The CTS is also a time-consuming process for checking the clock tree. If the chip design and specification do not match, the CTS result will be wrong. Many users use licensed electronic desig...
Main Authors: | Nayoung Kwon, Daejin Park |
---|---|
Format: | Article |
Language: | English |
Published: |
MDPI AG
2023-10-01
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Series: | Electronics |
Subjects: | |
Online Access: | https://www.mdpi.com/2079-9292/12/20/4340 |
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