Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

Perfect Concurrent Fault Detection in CMOS Logic Circuits Using Parity Preservative Reversible Gates

Reversible logic has 100% fault observability meaning that a fault in any circuit node propagates to the output stage. In other words, reversible circuits are latent-fault-free. Our motivation is to incorporate this unique feature of reversible logic to design CMOS circuits having perfect or 100% Co...

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Bibliographic Details
Main Authors: Sajjad Parvin, Mustafa Altun
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Access
Subjects:
Reversible logic
fault preservation
latent faults
fault tolerant CMOS
concurrent error detection
QCA
Online Access:https://ieeexplore.ieee.org/document/8890724/

Internet

https://ieeexplore.ieee.org/document/8890724/

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