Macro Model for Discrete-Time Sigma‒Delta Modulators
This work presents a macro model for discrete-time sigma‒delta modulators, which can significantly reduce the simulation time compared to transistor level circuits. The proposed macro model is realized by effectively combining active and passive ideal circuit components with Verilog-A modules. As su...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-12-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/11/23/3994 |