Design of Efficient Phase Locked Loop for Low Power Applications

Design of Efficient Phase Locked Loop for Low Power Applications

The phase-locked loop is a technique that has contributed significantly to technological advancements in many applications in the fast-evolving digital era. In this paper, a Phase Locked Loop (PLL) is designed using 90 nm CMOS technology node with 1.8 V supply voltage. It features a PLL design with...

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Bibliographic Details
Main Authors: Chandra Keerthi Pothina, Ngangbam Phalguni Singh, Jagupilla Lakshmi Prasanna, Chella Santhosh, Mokkapati Ravi Kumar
Format: Article
Language:English
Published: MDPI AG 2023-03-01
Series:Engineering Proceedings
Subjects:
Phase Locked Loop (PLL)
Phase Frequency Detector/Charge Pump (PFD/CP)
Low Pass Filter (LPF)
Current Starved Voltage-Controlled Oscillator (CSVCO)
Analog Digital Environment (ADE)
Online Access:https://www.mdpi.com/2673-4591/34/1/14

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https://www.mdpi.com/2673-4591/34/1/14

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