Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters

Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters

Real-time simulation is important for ensuring the reliable operation of VSC-HVDC converters in power grids, particularly through the use of rapid control prototyping (RCP) and hardware-in-the-loop (HIL) based converter controllers. While real-time simulation is a common practice for modular multile...

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Bibliographic Details
Main Authors: Levi Bieber, Liwei Wang, Juri Jatskevich, Wei Li
Format: Article
Language:English
Published: IEEE 2023-01-01
Series:IEEE Access
Subjects:
FPGA
hybrid multilevel converter
modular multilevel converter (MMC)
rapid control prototyping (RCP)
real-time simulation
voltage-source converter high voltage direct current (VSC-HVDC)
Online Access:https://ieeexplore.ieee.org/document/10011408/

Internet

https://ieeexplore.ieee.org/document/10011408/

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