Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters
Real-time simulation is important for ensuring the reliable operation of VSC-HVDC converters in power grids, particularly through the use of rapid control prototyping (RCP) and hardware-in-the-loop (HIL) based converter controllers. While real-time simulation is a common practice for modular multile...
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/10011408/ |
| _version_ | 1797902325521580032 |
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| author | Levi Bieber Liwei Wang Juri Jatskevich Wei Li |
| author_facet | Levi Bieber Liwei Wang Juri Jatskevich Wei Li |
| author_sort | Levi Bieber |
| collection | DOAJ |
| description | Real-time simulation is important for ensuring the reliable operation of VSC-HVDC converters in power grids, particularly through the use of rapid control prototyping (RCP) and hardware-in-the-loop (HIL) based converter controllers. While real-time simulation is a common practice for modular multilevel converters (MMCs), it has been less frequently applied to the new class of hybrid cascaded multilevel converters (HCMCs). In this study, a universal equivalent model (UEM) is proposed for a range of HCMC topologies that combines accuracy and computational efficiency through the use of both CPUs and field-programmable gate arrays (FPGAs). The proposed UEM is derived using the hybrid five-level converter (H5LC), a compact, efficient, and fault-tolerant VSC within the HCMC family. The UEM relies on CPUs to simulate the main circuits and controls of the main converter, and utilizes FPGAs to calculate the instantaneous voltages of a large number of full-bridge submodules (FBSMs), flying capacitors, and DC-side pole capacitors. In addition, the FBSMs’ voltage-balancing and switching algorithms are implemented on the FPGAs. The proposed real-time CPU/FPGA-based H5LC-UEM is compared to an offline CPU-based detailed equivalent model to verify its accuracy. |
| first_indexed | 2024-04-10T09:15:57Z |
| format | Article |
| id | doaj.art-de9e70339cb24167be626be95ebe9cbb |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-10T09:15:57Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-de9e70339cb24167be626be95ebe9cbb2023-02-21T00:00:56ZengIEEEIEEE Access2169-35362023-01-01114228424110.1109/ACCESS.2023.323527210011408Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel ConvertersLevi Bieber0https://orcid.org/0000-0001-9302-7226Liwei Wang1https://orcid.org/0000-0003-1076-5827Juri Jatskevich2https://orcid.org/0000-0002-3069-327XWei Li3https://orcid.org/0000-0001-6005-0892School of Engineering, The University of British Columbia, Okanagan Campus, Kelowna, CanadaSchool of Engineering, The University of British Columbia, Okanagan Campus, Kelowna, CanadaDepartment of Electrical and Computer Engineering, The University of British Columbia, Vancouver, CanadaOPAL-RT Technologies, Montreal, CanadaReal-time simulation is important for ensuring the reliable operation of VSC-HVDC converters in power grids, particularly through the use of rapid control prototyping (RCP) and hardware-in-the-loop (HIL) based converter controllers. While real-time simulation is a common practice for modular multilevel converters (MMCs), it has been less frequently applied to the new class of hybrid cascaded multilevel converters (HCMCs). In this study, a universal equivalent model (UEM) is proposed for a range of HCMC topologies that combines accuracy and computational efficiency through the use of both CPUs and field-programmable gate arrays (FPGAs). The proposed UEM is derived using the hybrid five-level converter (H5LC), a compact, efficient, and fault-tolerant VSC within the HCMC family. The UEM relies on CPUs to simulate the main circuits and controls of the main converter, and utilizes FPGAs to calculate the instantaneous voltages of a large number of full-bridge submodules (FBSMs), flying capacitors, and DC-side pole capacitors. In addition, the FBSMs’ voltage-balancing and switching algorithms are implemented on the FPGAs. The proposed real-time CPU/FPGA-based H5LC-UEM is compared to an offline CPU-based detailed equivalent model to verify its accuracy.https://ieeexplore.ieee.org/document/10011408/FPGAhybrid multilevel convertermodular multilevel converter (MMC)rapid control prototyping (RCP)real-time simulationvoltage-source converter high voltage direct current (VSC-HVDC) |
| spellingShingle | Levi Bieber Liwei Wang Juri Jatskevich Wei Li Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters IEEE Access FPGA hybrid multilevel converter modular multilevel converter (MMC) rapid control prototyping (RCP) real-time simulation voltage-source converter high voltage direct current (VSC-HVDC) |
| title | Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters |
| title_full | Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters |
| title_fullStr | Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters |
| title_full_unstemmed | Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters |
| title_short | Universal Equivalent Model for Real-Time CPU/FPGA Co-Simulation of Hybrid Cascaded Multilevel Converters |
| title_sort | universal equivalent model for real time cpu fpga co simulation of hybrid cascaded multilevel converters |
| topic | FPGA hybrid multilevel converter modular multilevel converter (MMC) rapid control prototyping (RCP) real-time simulation voltage-source converter high voltage direct current (VSC-HVDC) |
| url | https://ieeexplore.ieee.org/document/10011408/ |
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