Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction
Abstract The continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2023-08-01
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| Series: | The Journal of Engineering |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/tje2.12296 |