Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction
Abstract The continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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Wiley
2023-08-01
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| Series: | The Journal of Engineering |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/tje2.12296 |
| _version_ | 1797736781441925120 |
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| author | Naga Venkata Vijaya Krishna Boppana Saiyu Ren |
| author_facet | Naga Venkata Vijaya Krishna Boppana Saiyu Ren |
| author_sort | Naga Venkata Vijaya Krishna Boppana |
| collection | DOAJ |
| description | Abstract The continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre‐computation stage constitutes magnitude calculation and non‐trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8×8, 16×16, 32×32, and 64×64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power‐delay‐product of synthesized and post‐layout designs using 32 nm CMOS technology with 1.05 V supply voltage. |
| first_indexed | 2024-03-12T13:18:54Z |
| format | Article |
| id | doaj.art-dea41d71b630484b91ef8c10c254185e |
| institution | Directory Open Access Journal |
| issn | 2051-3305 |
| language | English |
| last_indexed | 2024-03-12T13:18:54Z |
| publishDate | 2023-08-01 |
| publisher | Wiley |
| record_format | Article |
| series | The Journal of Engineering |
| spelling | doaj.art-dea41d71b630484b91ef8c10c254185e2023-08-26T10:20:50ZengWileyThe Journal of Engineering2051-33052023-08-0120238n/an/a10.1049/tje2.12296Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reductionNaga Venkata Vijaya Krishna Boppana0Saiyu Ren1Department of Electrical Engineering Wright State University College of Engineering and Computer Science DaytonOhioUSADepartment of Electrical Engineering Wright State University College of Engineering and Computer Science DaytonOhioUSAAbstract The continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using magnitudes of the multiplicand and the multiplier. The pre‐computation stage constitutes magnitude calculation and non‐trivial computations required to generate partial products. A new partial product reduction strategy is deployed in the design to improve the speed with low cost. 8×8, 16×16, 32×32, and 64×64 designs are presented for the proposed architectures. Performance results include area, power, delay, and power‐delay‐product of synthesized and post‐layout designs using 32 nm CMOS technology with 1.05 V supply voltage.https://doi.org/10.1049/tje2.12296CMOS digital integrated circuitsdigital integrated circuitslow‐power electronics |
| spellingShingle | Naga Venkata Vijaya Krishna Boppana Saiyu Ren Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction The Journal of Engineering CMOS digital integrated circuits digital integrated circuits low‐power electronics |
| title | Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction |
| title_full | Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction |
| title_fullStr | Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction |
| title_full_unstemmed | Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction |
| title_short | Simple low power‐delay‐product parallel signed multiplier design using radix‐8 structure with efficient partial product reduction |
| title_sort | simple low power delay product parallel signed multiplier design using radix 8 structure with efficient partial product reduction |
| topic | CMOS digital integrated circuits digital integrated circuits low‐power electronics |
| url | https://doi.org/10.1049/tje2.12296 |
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