Design of carrylook-ahead adder at switch level(超前进位全加器的开关级设计)

应用CMOS电路开关级设计技术对超前进位全加器进行了设计,并用PSPICE模拟进行了功能验证.与传统门级设计电路相比,本文设计的超前进位电路使用了较少的MOS管,并能保持原有的传输延迟.

Bibliographic Details
Main Authors:	SHENYan-fei(沈雁飞), WUXun-wei(吴训威)
Format:	Article
Language:	zho
Published:	Zhejiang University Press 2003-05-01
Series:	Zhejiang Daxue xuebao. Lixue ban
Subjects:	开关级设计超前进位全加器
Online Access:	https://doi.org/zjup/1008-9497.2003.30.3.277-280

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