Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology

In this paper problem is addressed in the current study by providing resource-efficient CORDIC enabled neuron architecture (RECON) that can be customized to calculate both block of multiply-accumulate (MAC) unit and non-linear activation function (AF) operations. The CORDIC-enabled architecture impl...

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Bibliographic Details
Main Authors: Vijay Pratap Sharma, Hemant Patidar, Gopal Raut, Vikas Maheshwari, Rajib Kar
Format: Article
Language:English
Published: Elsevier 2023-06-01
Series:e-Prime: Advances in Electrical Engineering, Electronics and Energy
Subjects:
Online Access:http://www.sciencedirect.com/science/article/pii/S2772671123000529