Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology
In this paper problem is addressed in the current study by providing resource-efficient CORDIC enabled neuron architecture (RECON) that can be customized to calculate both block of multiply-accumulate (MAC) unit and non-linear activation function (AF) operations. The CORDIC-enabled architecture impl...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Elsevier
2023-06-01
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| Series: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2772671123000529 |
| _version_ | 1797802074118815744 |
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| author | Vijay Pratap Sharma Hemant Patidar Gopal Raut Vikas Maheshwari Rajib Kar |
| author_facet | Vijay Pratap Sharma Hemant Patidar Gopal Raut Vikas Maheshwari Rajib Kar |
| author_sort | Vijay Pratap Sharma |
| collection | DOAJ |
| description | In this paper problem is addressed in the current study by providing resource-efficient CORDIC enabled neuron architecture (RECON) that can be customized to calculate both block of multiply-accumulate (MAC) unit and non-linear activation function (AF) operations. The CORDIC-enabled architecture implements MAC and AF operations using linear and trigonometric relationships, respectively. All physical parameters of the proposed design are built and verified using Cadence Virtuoso @ 45 nm technology. As compared to the conventional art of MAC design, our implementation of the signed fixed-point 8-bit MAC results in a 70% reduction in area, latency, and power product (ALP), as well as a 45 percent reduction in area, a 28% reduction in power dissipation, and a 20% reduction in latency. Both the process adjustments and the device mismatch are subjected to Monte-Carlo simulations. The proposed design is based on resource-intensive components such as multipliers and non-linear Activation Functions, modern hardware implementations of DNNs require more space (AFs). To access input features, weights, and biases, and improved on-chip quantized log2 based memory addressing approach is implemented. The bandwidth needs of DNNs' external memory are therefore decreased and dynamically adjusted. The Taylor series is also used to extract intensive higher speed and resource-efficient memory components for the various activation functions, and its order expansion has been altered for increased test accuracy. The MNIST dataset is used in earlier studies. |
| first_indexed | 2024-03-13T05:01:12Z |
| format | Article |
| id | doaj.art-df33d0526075407cbc5efc11ad5d984a |
| institution | Directory Open Access Journal |
| issn | 2772-6711 |
| language | English |
| last_indexed | 2024-03-13T05:01:12Z |
| publishDate | 2023-06-01 |
| publisher | Elsevier |
| record_format | Article |
| series | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| spelling | doaj.art-df33d0526075407cbc5efc11ad5d984a2023-06-17T05:21:50ZengElseviere-Prime: Advances in Electrical Engineering, Electronics and Energy2772-67112023-06-014100157Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technologyVijay Pratap Sharma0Hemant Patidar1Gopal Raut2Vikas Maheshwari3Rajib Kar4Department of Electronics & Communication Engineering, Oriental University, Indore (M. P.) 453555, IndiaDepartment of Electronics & Communication Engineering, Oriental University, Indore (M. P.) 453555, India; Corresponding author.Department of Electrical Engineering, IIT, Indore (M. P.) 453552, IndiaDepartment of Electronics and Communication Engineering, Guru Nanak Institutions, Hyderabad, IndiaDepartment of Electronics and Communication Engineering, NIT, Durgapur, W.B., IndiaIn this paper problem is addressed in the current study by providing resource-efficient CORDIC enabled neuron architecture (RECON) that can be customized to calculate both block of multiply-accumulate (MAC) unit and non-linear activation function (AF) operations. The CORDIC-enabled architecture implements MAC and AF operations using linear and trigonometric relationships, respectively. All physical parameters of the proposed design are built and verified using Cadence Virtuoso @ 45 nm technology. As compared to the conventional art of MAC design, our implementation of the signed fixed-point 8-bit MAC results in a 70% reduction in area, latency, and power product (ALP), as well as a 45 percent reduction in area, a 28% reduction in power dissipation, and a 20% reduction in latency. Both the process adjustments and the device mismatch are subjected to Monte-Carlo simulations. The proposed design is based on resource-intensive components such as multipliers and non-linear Activation Functions, modern hardware implementations of DNNs require more space (AFs). To access input features, weights, and biases, and improved on-chip quantized log2 based memory addressing approach is implemented. The bandwidth needs of DNNs' external memory are therefore decreased and dynamically adjusted. The Taylor series is also used to extract intensive higher speed and resource-efficient memory components for the various activation functions, and its order expansion has been altered for increased test accuracy. The MNIST dataset is used in earlier studies.http://www.sciencedirect.com/science/article/pii/S2772671123000529Activation functionEmbedded AFCORDICConfigurable architectureMACNeural network |
| spellingShingle | Vijay Pratap Sharma Hemant Patidar Gopal Raut Vikas Maheshwari Rajib Kar Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology e-Prime: Advances in Electrical Engineering, Electronics and Energy Activation function Embedded AF CORDIC Configurable architecture MAC Neural network |
| title | Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology |
| title_full | Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology |
| title_fullStr | Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology |
| title_full_unstemmed | Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology |
| title_short | Low power resource efficient CORDIC enabled neuron architecture using 45 nm CMOS technology |
| title_sort | low power resource efficient cordic enabled neuron architecture using 45 nm cmos technology |
| topic | Activation function Embedded AF CORDIC Configurable architecture MAC Neural network |
| url | http://www.sciencedirect.com/science/article/pii/S2772671123000529 |
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