Sharing of Topped-Off Compressed Test Sets Among Logic Blocks
Test data compression implies that a compressed test set is stored on a tester, and an on-chip decompression logic produces tests that can be applied to the circuit from compressed tests. Test data compression is used for reducing the test data volume and test application time. In a design that cons...
| Main Author: | |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2024-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10493003/ |