Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield

TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress....

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Bibliographic Details
Main Authors: Koji Sakui, Yisuo Li, Masakazu Kakumu, Kenichi Kanazawa, Iwao Kunishima, Yoshihisa Iwata, Nozomu Harada
Format: Article
Language:English
Published: Elsevier 2023-07-01
Series:Memories - Materials, Devices, Circuits and Systems
Subjects:
Surrounding Gate Transistor (SGT)
GAA
FinFET
SOI
1T-DRAM
Capacitorless DRAM
Online Access:http://www.sciencedirect.com/science/article/pii/S2773064623000312

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http://www.sciencedirect.com/science/article/pii/S2773064623000312

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