Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield
TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress....
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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Elsevier
2023-07-01
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| Series: | Memories - Materials, Devices, Circuits and Systems |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2773064623000312 |
| _version_ | 1827917363061719040 |
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| author | Koji Sakui Yisuo Li Masakazu Kakumu Kenichi Kanazawa Iwao Kunishima Yoshihisa Iwata Nozomu Harada |
| author_facet | Koji Sakui Yisuo Li Masakazu Kakumu Kenichi Kanazawa Iwao Kunishima Yoshihisa Iwata Nozomu Harada |
| author_sort | Koji Sakui |
| collection | DOAJ |
| description | TCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current. |
| first_indexed | 2024-03-13T03:27:45Z |
| format | Article |
| id | doaj.art-df904d1b986e4b529f397be2a560af26 |
| institution | Directory Open Access Journal |
| issn | 2773-0646 |
| language | English |
| last_indexed | 2024-03-13T03:27:45Z |
| publishDate | 2023-07-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Memories - Materials, Devices, Circuits and Systems |
| spelling | doaj.art-df904d1b986e4b529f397be2a560af262023-06-25T04:45:13ZengElsevierMemories - Materials, Devices, Circuits and Systems2773-06462023-07-014100054Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shieldKoji Sakui0Yisuo Li1Masakazu Kakumu2Kenichi Kanazawa3Iwao Kunishima4Yoshihisa Iwata5Nozomu Harada6Corresponding author.; Unisantis Electronics Singapore, 60 Paya Lebar Road, #10-49 Paya Lebar Square, Singapore 409051, SingaporeUnisantis Electronics Singapore, 60 Paya Lebar Road, #10-49 Paya Lebar Square, Singapore 409051, SingaporeUnisantis Electronics Singapore, 60 Paya Lebar Road, #10-49 Paya Lebar Square, Singapore 409051, SingaporeUnisantis Electronics Singapore, 60 Paya Lebar Road, #10-49 Paya Lebar Square, Singapore 409051, SingaporeUnisantis Electronics Singapore, 60 Paya Lebar Road, #10-49 Paya Lebar Square, Singapore 409051, SingaporeUnisantis Electronics Singapore, 60 Paya Lebar Road, #10-49 Paya Lebar Square, Singapore 409051, SingaporeUnisantis Electronics Singapore, 60 Paya Lebar Road, #10-49 Paya Lebar Square, Singapore 409051, SingaporeTCAD simulation using Silvaco software has shown that the 3G_DFM, which has SG1 (Select Gate 1), PL (Plate Line Gate), and SG2 (Select Gate 2) between SL (Source Line) and BL (Bit Line), has a long retention time of 100ms at 85 °C, and a robust disturbance shield which is a thousand times BL stress. The two select gates SG1 and SG2 protect the recombination of holes in the FB (Floating Body) at the SL and BL pn-junctions, and shield the BL stress arising during other page operations, which leads to the GIDL (Gate Induced Drain Leakage) current.http://www.sciencedirect.com/science/article/pii/S2773064623000312Surrounding Gate Transistor (SGT)GAAFinFETSOI1T-DRAMCapacitorless DRAM |
| spellingShingle | Koji Sakui Yisuo Li Masakazu Kakumu Kenichi Kanazawa Iwao Kunishima Yoshihisa Iwata Nozomu Harada Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield Memories - Materials, Devices, Circuits and Systems Surrounding Gate Transistor (SGT) GAA FinFET SOI 1T-DRAM Capacitorless DRAM |
| title | Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield |
| title_full | Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield |
| title_fullStr | Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield |
| title_full_unstemmed | Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield |
| title_short | Design impact on three gate Dynamic Flash Memory (3G_DFM) for long hole retention time and robust disturbance shield |
| title_sort | design impact on three gate dynamic flash memory 3g dfm for long hole retention time and robust disturbance shield |
| topic | Surrounding Gate Transistor (SGT) GAA FinFET SOI 1T-DRAM Capacitorless DRAM |
| url | http://www.sciencedirect.com/science/article/pii/S2773064623000312 |
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