High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits
Abstract Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/...
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| Format: | Article |
| Language: | English |
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Nature Portfolio
2017-05-01
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| Series: | Scientific Reports |
| Online Access: | https://doi.org/10.1038/s41598-017-01012-y |
| _version_ | 1818343957628715008 |
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| author | Tsung-Ta Wu Wen-Hsien Huang Chih-Chao Yang Hung-Chun Chen Tung-Ying Hsieh Wei-Sheng Lin Ming-Hsuan Kao Chiu-Hao Chen Jie-Yi Yao Yi-Ling Jian Chiung-Chih Hsu Kun-Lin Lin Chang-Hong Shen Yu-Lun Chueh Jia-Min Shieh |
| author_facet | Tsung-Ta Wu Wen-Hsien Huang Chih-Chao Yang Hung-Chun Chen Tung-Ying Hsieh Wei-Sheng Lin Ming-Hsuan Kao Chiu-Hao Chen Jie-Yi Yao Yi-Ling Jian Chiung-Chih Hsu Kun-Lin Lin Chang-Hong Shen Yu-Lun Chueh Jia-Min Shieh |
| author_sort | Tsung-Ta Wu |
| collection | DOAJ |
| description | Abstract Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate. |
| first_indexed | 2024-12-13T16:38:50Z |
| format | Article |
| id | doaj.art-dfca7c0d50a149839d75f7508a8ac08d |
| institution | Directory Open Access Journal |
| issn | 2045-2322 |
| language | English |
| last_indexed | 2024-12-13T16:38:50Z |
| publishDate | 2017-05-01 |
| publisher | Nature Portfolio |
| record_format | Article |
| series | Scientific Reports |
| spelling | doaj.art-dfca7c0d50a149839d75f7508a8ac08d2022-12-21T23:38:20ZengNature PortfolioScientific Reports2045-23222017-05-017111110.1038/s41598-017-01012-yHigh Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) CircuitsTsung-Ta Wu0Wen-Hsien Huang1Chih-Chao Yang2Hung-Chun Chen3Tung-Ying Hsieh4Wei-Sheng Lin5Ming-Hsuan Kao6Chiu-Hao Chen7Jie-Yi Yao8Yi-Ling Jian9Chiung-Chih Hsu10Kun-Lin Lin11Chang-Hong Shen12Yu-Lun Chueh13Jia-Min Shieh14National Nano Device LaboratoriesNational Nano Device LaboratoriesNational Nano Device LaboratoriesNational Nano Device LaboratoriesNational Nano Device LaboratoriesDepartment of Materials Science and Engineering, National Tsing Hua UniversityDepartments of Photonics and Institute of Electro-Optical Engineering, National Chiao-Tung UniversityNational Nano Device LaboratoriesNational Nano Device LaboratoriesNational Nano Device LaboratoriesNational Nano Device LaboratoriesNational Nano Device LaboratoriesNational Nano Device LaboratoriesDepartment of Materials Science and Engineering, National Tsing Hua UniversityNational Nano Device LaboratoriesAbstract Development of manufacture trend for TFTs technologies has focused on improving electrical properties of films with the cost reduction to achieve commercialization. To achieve this goal, high-performance sub-50 nm TFTs-based MOSFETs with ON-current (Ion)/subthreshold swing (S.S.) of 181 µA/µm/107 mV/dec and 188 µA/µm/98 mV/dec for NMOSFETs and PMOSFETs in a monolithic 3D circuit were demonstrated by a low power with low thermal budget process. In addition, a stackable static random access memory (SRAM) integrated with TFTs-based MOSFET with static noise margins (SNM) equals to 390 mV at VDD = 1.0 V was demonstrated. Overall processes include a low thermal budget via ultra-flat and ultra-thin poly-Si channels by solid state laser crystallization process, chemical-mechanical polishing (CMP) planarization, plasma-enhanced atomic layer deposition (ALD) gate stacking layers and infrared laser activation with a low thermal budget. Detailed material and electrical properties were investigated. The advanced 3D architecture with closely spaced inter-layer dielectrics (ILD) enables high-performance stackable MOSFETs and SRAM for power-saving IoT/mobile products at a low cost or flexible substrate.https://doi.org/10.1038/s41598-017-01012-y |
| spellingShingle | Tsung-Ta Wu Wen-Hsien Huang Chih-Chao Yang Hung-Chun Chen Tung-Ying Hsieh Wei-Sheng Lin Ming-Hsuan Kao Chiu-Hao Chen Jie-Yi Yao Yi-Ling Jian Chiung-Chih Hsu Kun-Lin Lin Chang-Hong Shen Yu-Lun Chueh Jia-Min Shieh High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits Scientific Reports |
| title | High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits |
| title_full | High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits |
| title_fullStr | High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits |
| title_full_unstemmed | High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits |
| title_short | High Performance and Low power Monolithic Three-Dimensional Sub-50 nm Poly Si Thin film transistor (TFTs) Circuits |
| title_sort | high performance and low power monolithic three dimensional sub 50 nm poly si thin film transistor tfts circuits |
| url | https://doi.org/10.1038/s41598-017-01012-y |
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