A passive second‐order noise‐shaping SAR ADC architecture with increased freedom in NTF synthesis and relaxed clock‐jitter issue
Abstract Noise‐shaping (NS) successive approximation register (SAR) analogue‐to‐digital converters (ADCs) are an attractive architecture for power and area efficiency in moderate resolution and bandwidth applications. NS SAR ADCs employing a passive integrator are good candidates for their omission...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2022-07-01
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| Series: | Electronics Letters |
| Online Access: | https://doi.org/10.1049/ell2.12518 |