Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision
Abstract Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, te...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Hindawi-IET
2022-03-01
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| Series: | IET Circuits, Devices and Systems |
| Subjects: | |
| Online Access: | https://doi.org/10.1049/cds2.12093 |
| _version_ | 1797422470140002304 |
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| author | Deruo Cheng Yiqiong Shi Tong Lin Bah‐Hwee Gwee Kar‐Ann Toh |
| author_facet | Deruo Cheng Yiqiong Shi Tong Lin Bah‐Hwee Gwee Kar‐Ann Toh |
| author_sort | Deruo Cheng |
| collection | DOAJ |
| description | Abstract Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques that require less human intervention are desired. In this paper, we propose a template‐based Tanimoto Convolution and Morphological Decision (TCMD) model for transistor interconnection retrieval in delayered ICs, that is, poly line segmentation, with minimal human intervention. In our proposed TCMD model, prior domain knowledge on the IC images is incorporated into the proposed Tanimoto convolution for generating input feature maps, eliminating the need of filter learning. We further propose morphological decision to process the input feature maps for higher accuracy and robustness on determining poly line positions. With experiments on a delayered IC @90 nm process, our proposed TCMD model achieves 3%∼6% higher accuracy than the reported template‐based techniques. Our proposed TCMD model also achieves competitive accuracy with the reported deep U‐net while requiring 13× shorter training/validation time. To further improve the pixel‐wise precision of the retrieved poly lines, which is important for applications such as analog circuit analysis, we propose a deep learning‐based TCMD‐PL model. The proposed TCMD‐PL model utilises the output of TCMD model as the pseudo labels for training a deep convolutional neural network in supervised manner, and it is able to achieve further performance improvement of ∼4% in comparison to TCMD model without extra data labelling. |
| first_indexed | 2024-03-09T07:32:45Z |
| format | Article |
| id | doaj.art-e1fe3597e33b46feb303c78b6a17a3ac |
| institution | Directory Open Access Journal |
| issn | 1751-858X 1751-8598 |
| language | English |
| last_indexed | 2024-03-09T07:32:45Z |
| publishDate | 2022-03-01 |
| publisher | Hindawi-IET |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj.art-e1fe3597e33b46feb303c78b6a17a3ac2023-12-03T05:59:26ZengHindawi-IETIET Circuits, Devices and Systems1751-858X1751-85982022-03-0116216917710.1049/cds2.12093Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological DecisionDeruo Cheng0Yiqiong Shi1Tong Lin2Bah‐Hwee Gwee3Kar‐Ann Toh4School of Electrical and Electronic Engineering Nanyang Technological University of Singapore SingaporeSchool of Electrical and Electronic Engineering Nanyang Technological University of Singapore SingaporeSchool of Electrical and Electronic Engineering Nanyang Technological University of Singapore SingaporeSchool of Electrical and Electronic Engineering Nanyang Technological University of Singapore SingaporeSchool of Electrical and Electronic Engineering Yonsei University Seoul South KoreaAbstract Supervised machine learning techniques are being pursued for delayered Integrated Circuit (IC) image analysis. However, repetitive data labelling and model training are required for every image set with the supervised techniques. In view of the large scale of IC image set being analysed, techniques that require less human intervention are desired. In this paper, we propose a template‐based Tanimoto Convolution and Morphological Decision (TCMD) model for transistor interconnection retrieval in delayered ICs, that is, poly line segmentation, with minimal human intervention. In our proposed TCMD model, prior domain knowledge on the IC images is incorporated into the proposed Tanimoto convolution for generating input feature maps, eliminating the need of filter learning. We further propose morphological decision to process the input feature maps for higher accuracy and robustness on determining poly line positions. With experiments on a delayered IC @90 nm process, our proposed TCMD model achieves 3%∼6% higher accuracy than the reported template‐based techniques. Our proposed TCMD model also achieves competitive accuracy with the reported deep U‐net while requiring 13× shorter training/validation time. To further improve the pixel‐wise precision of the retrieved poly lines, which is important for applications such as analog circuit analysis, we propose a deep learning‐based TCMD‐PL model. The proposed TCMD‐PL model utilises the output of TCMD model as the pseudo labels for training a deep convolutional neural network in supervised manner, and it is able to achieve further performance improvement of ∼4% in comparison to TCMD model without extra data labelling.https://doi.org/10.1049/cds2.12093image segmentationdeep learning (artificial intelligence)convolutional neural netssupervised learningcircuit analysis computingintegrated circuits |
| spellingShingle | Deruo Cheng Yiqiong Shi Tong Lin Bah‐Hwee Gwee Kar‐Ann Toh Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision IET Circuits, Devices and Systems image segmentation deep learning (artificial intelligence) convolutional neural nets supervised learning circuit analysis computing integrated circuits |
| title | Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision |
| title_full | Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision |
| title_fullStr | Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision |
| title_full_unstemmed | Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision |
| title_short | Delayered IC image analysis with template‐based Tanimoto Convolution and Morphological Decision |
| title_sort | delayered ic image analysis with template based tanimoto convolution and morphological decision |
| topic | image segmentation deep learning (artificial intelligence) convolutional neural nets supervised learning circuit analysis computing integrated circuits |
| url | https://doi.org/10.1049/cds2.12093 |
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