Efficiency of Priority Queue Architectures in FPGA

Efficiency of Priority Queue Architectures in FPGA

This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC. The proposed architecture is based on shift registers, systolic arrays and SRAM memories. Such architecture, called MultiQueue, is optimi...

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Bibliographic Details
Main Author: Lukáš Kohútka
Format: Article
Language:English
Published: MDPI AG 2022-07-01
Series:Journal of Low Power Electronics and Applications
Subjects:
priority queue
architecture
efficiency
FPGA
SRAM
data sorting
Online Access:https://www.mdpi.com/2079-9268/12/3/39

Internet

https://www.mdpi.com/2079-9268/12/3/39

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