Efficiency of Priority Queue Architectures in FPGA
This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC. The proposed architecture is based on shift registers, systolic arrays and SRAM memories. Such architecture, called MultiQueue, is optimi...
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-07-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | https://www.mdpi.com/2079-9268/12/3/39 |