Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors

Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors

A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400-900 s). Subthreshold characteristics are improved and I<sub>off</sub> is drastically reduced (...

Full description

Bibliographic Details
Main Authors: Chris Chun-Chih Chung, Chun-Ming Ko, Tien-Sheng Chao
Format: Article
Language:English
Published: IEEE 2019-01-01
Series:IEEE Journal of the Electron Devices Society
Subjects:
Self-Limit
low-temperature trimming
fully silicided-S/D
vertically stacked
poly-Si
junctionless
Online Access:https://ieeexplore.ieee.org/document/8843925/

Internet

https://ieeexplore.ieee.org/document/8843925/

Similar Items