Self-Limited Low-Temperature Trimming and Fully Silicided S/D for Vertically Stacked Cantilever Gate-All-Around Poly-Si Junctionless Nanosheet Transistors
A self-limited low-temperature trimming process is demonstrated without surface morphology degradation. It shows great potential to control the trimming process with a large process window (400-900 s). Subthreshold characteristics are improved and I<sub>off</sub> is drastically reduced (...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2019-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8843925/ |