A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

A 45 nm Stacked CMOS Image Sensor Process Technology for Submicron Pixel

A submicron pixel’s light and dark performance were studied by experiment and simulation. An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is promising in that it may enhance performance. In this work, we demonstrated a low dark current of 3.2 e−/s at 60 °C, an ultra-l...

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Bibliographic Details
Main Authors: Seiji Takahashi, Yi-Min Huang, Jhy-Jyi Sze, Tung-Ting Wu, Fu-Sheng Guo, Wei-Cheng Hsu, Tung-Hsiung Tseng, King Liao, Chin-Chia Kuo, Tzu-Hsiang Chen, Wei-Chieh Chiang, Chun-Hao Chuang, Keng-Yu Chou, Chi-Hsien Chung, Kuo-Yu Chou, Chien-Hsien Tseng, Chuan-Joung Wang, Dun-Nien Yaung
Format: Article
Language:English
Published: MDPI AG 2017-12-01
Series:Sensors
Subjects:
submicron pixel
image sensor
stacked CMOS image sensor
dark current
read noise
random telegraph noise
full well capacity
optical crosstalk
Online Access:https://www.mdpi.com/1424-8220/17/12/2816

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https://www.mdpi.com/1424-8220/17/12/2816

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