Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET
In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without ch...
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MDPI AG
2023-01-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/14/2/301 |
| _version_ | 1797619269582716928 |
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| author | Chan Shan Lan Yang Ying Liu Zi-Meng Liu Han Zheng |
| author_facet | Chan Shan Lan Yang Ying Liu Zi-Meng Liu Han Zheng |
| author_sort | Chan Shan |
| collection | DOAJ |
| description | In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without chemically doped junctions by applying the polarity bias concept to a doped N<sup>+</sup>/P<sup>−</sup> starting structure. Using numerical device simulations, we demonstrate how the tunneling barrier width on the drain side can be influenced by several design parameters, such as the gap length between the channel and the drain (L<sub>gap</sub>), the working function of the polarity gate, and the dielectric material of the spacer. The simulation results show that an ED PNPN tunneling FET with an ED drain, which has been explored for the first time, exhibits a low ambipolar current of 5.87 × 10<sup>−16</sup> A/µm at a gap length of 20 nm. The ambipolar current is reduced by six orders of magnitude compared to that which occurs with a conventional ED PNPN tunnel FET with a uniformly doped drain, while the average subthreshold slope and the ON state and OFF state currents remained nearly identical. |
| first_indexed | 2024-03-11T08:25:46Z |
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| id | doaj.art-e98a33d8b4154665aae1bf9f7e7bc113 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-11T08:25:46Z |
| publishDate | 2023-01-01 |
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| spelling | doaj.art-e98a33d8b4154665aae1bf9f7e7bc1132023-11-16T22:10:20ZengMDPI AGMicromachines2072-666X2023-01-0114230110.3390/mi14020301Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FETChan Shan0Lan Yang1Ying Liu2Zi-Meng Liu3Han Zheng4College of Ocean Information Engineering, Jimei University, Xiamen 361021, ChinaCollege of Software, Quanzhou University of Information Engineering, Quanzhou 362000, ChinaDepartment of Software Technology, Xiamen Institute of Software Technology, Xiamen 361021, ChinaDepartment of Software Technology, Xiamen Institute of Software Technology, Xiamen 361021, ChinaDepartment of Software Technology, Xiamen Institute of Software Technology, Xiamen 361021, ChinaIn this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without chemically doped junctions by applying the polarity bias concept to a doped N<sup>+</sup>/P<sup>−</sup> starting structure. Using numerical device simulations, we demonstrate how the tunneling barrier width on the drain side can be influenced by several design parameters, such as the gap length between the channel and the drain (L<sub>gap</sub>), the working function of the polarity gate, and the dielectric material of the spacer. The simulation results show that an ED PNPN tunneling FET with an ED drain, which has been explored for the first time, exhibits a low ambipolar current of 5.87 × 10<sup>−16</sup> A/µm at a gap length of 20 nm. The ambipolar current is reduced by six orders of magnitude compared to that which occurs with a conventional ED PNPN tunnel FET with a uniformly doped drain, while the average subthreshold slope and the ON state and OFF state currents remained nearly identical.https://www.mdpi.com/2072-666X/14/2/301electrically dopingPNPN tunnel FETambipolar currenttunneling barrier widthTCAD simulation |
| spellingShingle | Chan Shan Lan Yang Ying Liu Zi-Meng Liu Han Zheng Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET Micromachines electrically doping PNPN tunnel FET ambipolar current tunneling barrier width TCAD simulation |
| title | Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET |
| title_full | Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET |
| title_fullStr | Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET |
| title_full_unstemmed | Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET |
| title_short | Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET |
| title_sort | controlling drain side tunneling barrier width in electrically doped pnpn tunnel fet |
| topic | electrically doping PNPN tunnel FET ambipolar current tunneling barrier width TCAD simulation |
| url | https://www.mdpi.com/2072-666X/14/2/301 |
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