A Silicon Biristor With Reduced Operating Voltage: Proposal and Analysis
In this paper, using 2-D simulations, we report a silicon biristor with reduced operating voltage using the surface accumulation layer transistor (SALTran) concept. The electrical characteristics of the proposed SALTran biristor are simulated and compared with that of a conventional silicon biristor...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2015-01-01
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| Series: | IEEE Journal of the Electron Devices Society |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/6994257/ |