A Parallelized Implementation of Turbo Decoding Based on Network on Chip Multi-core Processor
With the evolution of wireless communication systems, it is increasingly difficult for Application Specific Integrated Circuit (ASIC) solutions to meet the daily changing requirements. A network on chip (NOC) multi-core processor based on message-passing programming model is designed to implement...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Eastern Macedonia and Thrace Institute of Technology
2014-03-01
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| Series: | Journal of Engineering Science and Technology Review |
| Subjects: | |
| Online Access: | http://www.jestr.org/downloads/Volume7Issue1/fulltext97114.pdf |