Silicon Wafer CMP Slurry Using a Hydrolysis Reaction Accelerator with an Amine Functional Group Remarkably Enhances Polishing Rate

Recently, as an alternative solution for overcoming the scaling-down limitations of logic devices with design length of less than 3 nm and enhancing DRAM operation performance, 3D heterogeneous packaging technology has been intensively researched, essentially requiring Si wafer polishing at a very h...

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Bibliographic Details
Main Authors: Jae-Young Bae, Man-Hyup Han, Seung-Jae Lee, Eun-Seong Kim, Kyungsik Lee, Gon-sub Lee, Jin-Hyung Park, Jea-Gun Park
Format: Article
Language:English
Published: MDPI AG 2022-11-01
Series:Nanomaterials
Subjects:
Online Access:https://www.mdpi.com/2079-4991/12/21/3893